
Page 110 Pentek Model 6526 Operating Manual
Rev. A
3.8 ‘C31 DSP Memory Maps and Registers (continued)
3.8.8 Interrupt Vector Register − R/W @ ‘C31 Address 0xAX XX2X
This register is the interrupt vector for an interrupt from the ‘C31 DSP to a
VMEbus master. Table 3−71, below, shows this register’s bit layout. Bit V7 is
the most significant bit of the address.
3.8.9 Interrupt Mask Register − R/W @ ‘C31 Address 0xAX XX30
The interrupt mask register allows events or conditions to interrupt the ‘C31.
When the interrupt mask bit is set to logic '1', the event is enabled to cause an
interrupt. Once the interrupt event occurs, it is latched in the Interrupt Status
Register (see Section 3.8.10). Table 3−72, below, shows this register’s bit lay−
out. Table 3−73, below, identifies the interrupt condition for each bit.
Table 3−71: Interrupt Vector Register
R/W @ ‘C31 Address: 0xAX XX2X (X = "Don't Care" bits)
Bit # D15 – D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit Name Reserved − Not Used V7 V6 V5 V4 V3 V2 V1 V0
Function Write with Zeros, Mask when Reading Interrupt Vector
All bits default to the logic '0' state at power up and reset
Table 3−72: Interrupt Mask Register
R/W @ ‘C31 Address: 0xAX XX30 (X = "Don't Care" bits)
Bit # D15 – D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Bit Name Reserved − Not Used DPRU DPRL IFB IFA FIF CLKR CLKB CLKA TS OVLB OVLA
Function
Write with Zeros,
Mask when Reading
0 = Interrupt Disabled
1 = Interrupt Enabled
All bits default to the logic '0' state at power up and reset
Table 3−73: Interrupt Bit Conditions
Bit # Bit Name Interrupt Condition
D0 OVLA Input Channel A Overload Detector Interrupt
D1 OVLB Input Channel B Overload Detector Interrupt
D2 TS Time Stamp Interrupt
D3 CLKA Input Channel A Clock Loss Interrupt
D4 CLKB Input Channel B Clock Loss Interrupt
D5 CLKR Raceway Clock Loss Interrupt
D6 FIF Output FIFO Full / Formatter Sync Loss Interrupt (see NOTE, next page)
D7 IFA Input FIFO A Full Interrupt
D8 IFB Input FIFO B Full Interrupt
D9 DPRL Dual Port SRAM Mailbox (Lower Byte) Interrupt
D10 DPRU Dual Port SRAM Mailbox (Upper Byte) Interrupt
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