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Pentek Model 6526 Operating Manual Page 13

Rev. A

1.7 RACEway Interface

The Model 6526’s RACEway interface is implemented using the Cypress PitCREWjr chip

set. The RACEway interface circuitry creates separate RACEway packets for each DDR

on the board and sends them to the desired destination processors. Each DDR’s output

can be sent to one or more independent processors on another VME board in the same

VME chassis via RACEway Interlink Modules. For more information about RACEway

Interlinks, see Appendix B, and refer to the Pentek RACEway Handbook, Pentek part

number 800.00003.

The Model 6526 is directly compatible with all of Pentek’s RACEway−compatible DSP

processors, including the Models 4290 and 4291 (equipped with a Model 6219 or 6220

RACEway Interface VIM module) and the Model 4285 (equipped with the Option 034

RACEway interface). The Model 6526 supports local RACEway packet steering to any

of the processors on these boards, as determined by the RACEway address.

1.8 Digital Interfaces

Model 6526 Option 002 accepts two 16−bit differential ECL−level input signals, at a

maximum data rate of 62.5 MSPS. This input option is compatible with Pentek A/D

Converter Models 6402 Option 002, 6410 Option 002, 6425 Option 001, 6441 Option 002,

6465, 6470, and 6472. Model 6526 Option 019 accepts single−ended TTL−level signals,

at a maximum rate of 50 MSPS. This input option is compatible with the standard ver−

sions of Pentek A/D Converter Models 6402, 6410, 6420, 6425, and 6441.

Another input data source for the Model 6526 is the Watkins−Johnson WJ−9107 Wide−

band Telecom Tuner. The WJ−9107 output is a 36−pin connector delivering differential

ECL output levels. Two WJ−9107's may be located in an external VXI chassis, each

supplying one digitized data signal to the two data inputs on one Model 6526. A spe−

cial cable, available separately from Pentek as Model 2126, provides direct connection

for the two input data signals from two WJ−9107's to the Model 6526.

1.9 VMEbus Interface

The Model 6526 is a single−slot, VME stand−alone board that meets VME C.1 specifi−

cations. It provides slave A32/D32 access, A24/D16 access, and A16/D16 access. It

does not allow D8 access. It is a VMEbus interrupter but it is not a VMEbus interrupt

handler. It passes the Bus Grant and IACK daisy chain signals.

The VMEbus Slave Interface allows read/write control of registers and access to a dual

port SRAM used for passing parameters to the DDRs. These resources are memory

mapped into a unique A24/A32 VME address space. A second address space, identical

to the first, provides write−only access to all the same functions. The base address of

each of these two spaces is programmable in A16 address space. This allows multiple

boards to share the same write−only space for broadcast commands sent to several

boards using a single VMEbus cycle. Commands for individual boards can always be

sent through the unique read/write space.

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VXI?Corporation F80 Especificaciones Pagina 13