VXI?Corporation F80 Especificaciones descargar pdf (Pagina 57)

Pentek Model 6526 Operating Manual Page 57

Rev. A

3.5 VMEbus A24/A32 Global Slave Register Memory (continued)

3.5.9 Clock Status Register − R. O. @ Clock_Status

This register contains three read−only bits, which are used to indicate that the

associated clock signals are active. One bit is associated with the clock signal

on input A, another with the clock signal on input B, and the third is associ−

ated with the clock signal on the RACEway backplane fabric. For any of these

three bits, a logic '1' indicates that a clock signal is active on the associated

interface, and a logic '0' indicates that no clock signal is detected there. This

information is summarized in Table 3−17, below.

3.5.10 Input Data De−Skewing FIFOs

The Graychip GC4014 receivers require that all parallel data inputs to a given

receiver chip utilize the same clock signal. Since the Model 6526 uses two of

the four inputs on the GC4014, the clocks for each input must be at the same

frequency. Also, the clock edge to data transition relationship (data−to−clock

setup time) must be the same for both inputs to the receiver chip.

With data sources like the WJ−9107 (see Section 2.4.1.1), a clock is supplied

with each data channel. While the data−to−clock setup time may be main−

tained within each channel, there is no guarantee that the phase of the clocks

is maintained between two channels. In fact, the relative phase of the two

clocks will be initially different between two channels from the same WJ−9107

and will definitely be different between two WJ−9107’s, even though the two

units share a common frequency reference. In addition, the two channels will

be subject to phase differences because of cable length and will normally drift

in phase over time and temperature.

This would cause a significant problem for the GC4014 since it can only accept

a single clock for both data channels. In order to solve the problem, the Model

6526 incorporates dual−input FIFO memories. At the input, each of these

Input FIFOs accepts both clock and data from one of the two input sources.

Data is clocked out of both Input FIFOs and into the GC4014s by a common

clock (which can be either one of the two input clocks).

Table 3−17: Clock Status Register

R. O. @ Clock_Status

Bit # D31 – D3 D2 D1 D0

Bit Name R e s e r v e d − N o t U s e d

RACEway_

Clock_Status

Chan_A_

Clock_Status

Chan_B_

Clock_Status

Function

W r i t e w i t h z e r o s ,

M a s k w h e n r e a d i n g

1 = Active

0 = Not Active

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 195 196

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