VXI?Corporation F80 Especificaciones descargar pdf (Pagina 12)

Page 12 Pentek Model 6526 Operating Manual

Rev. A

1.4 Time Stamp Counter

The Time Stamp Counter is a 32−bit digital counter which acts as a master time code

reference for the board. It is used for time stamping data packets from the receivers,

and for determining when input switching commands are performed. It advances its

code using a nominal 10 µsec clock derived by dividing (pre−scaling) the input clock

from either parallel digital input.

1.5 Command Controller / DSP

The TMS320C31 Digital Signal Processor controls the receivers by using a list of input

switching times for each of the 16 channels. This list is written through the VMEbus

interface into a table, and then examined once every 10 µsec to determine if any DDR

channel should change its input switch setting for the current 32−bit time stamp.

1.6 Channel Formatters

Sixteen identical Channel Formatter sections accept serial output data from the GC4014

DDRs, convert the data to 32−bit parallel words, and then form data packets (blocks)

containing channel identification, the block number, the time stamp value, and a pro−

grammable number of complex DRR data samples. The channel identification and

block counter values are programmable over the VMEbus interface.

Optionally, the Channel Formatter also inserts a special Sync Code pattern into the data

sequence, replacing two consecutive DDR samples following the receipt of the Sync bus

signal for that channel.

Additionally, the Channel Formatter stores the RACEway routing code and the RACE−

way address for each channel into VME−programmable registers. This allows each

channel’s data packet to be directed to any RACEway board and then steered to any

resource on that board.

Data packets from the Channel Formatter are delivered to 4k x 32 synchronous Output

FIFOs, one for each of the 16 channels. Once a data packet is delivered to a FIFO, a sig−

nal is sent to the RACEway Controller. The RACEway Controller then retrieves the

RACEway routing code and address from the Channel Formatter, and starts a RACE−

way bus transfer using the packet stored in the FIFO.

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VXI?Corporation F80 Especificaciones Pagina 12