VXI?Corporation F80 Especificaciones descargar pdf (Pagina 189)

Interfacing to RACEway: PitCREWjr

The RACEway protocol communicates data direction in bit 1

of the address word. PitCREWjr’s slave state machine

branches on this bit value. If the direction of the data is from

the RACEway to the local FIFO, the transaction is a slave

write (bit 1 of address word is false). As data arrives from the

RACEway, it is registered and driven onto the FIFO data bus.

(See

Figure 2

.) The PitCREWjr writes the data received from

the RACEway to the output FIFO by asserting “OFWE

” each

time a valid word is ready on the FIFO data bus. A PitCREWjr

input called “OFAF

” is used to indicate to PitCREWjr that the

output FIFO is full. Assertion of “OFAF

” causes PitCREWjr to

send a kill request to the RACEway master, effectively ending

the RACEway transaction. “OFAF

” would typically be con-

nected to the output FIFO programmable almost full flag. On

completion of the RACEway data transfer, PitCREWjr

three-states the FIFO data bus and deasserts the “SLAVE”

status output.

If the direction of the data is from the input FIFO to the RACE-

way (a slave read, bit 1 of address word is true), then the FIFO

data bus is three-stated by PitCREWjr and PitCREWjr as-

serts the signal “IFRE

” and then “IFOE” to enable data from

the input FIFO onto the FIFO data bus. PitCREWjr asserts

this signal pair each time a new word is required from the

FIFO. If the input FIFO becomes empty, as signaled by the

“IFAE

” PitCREWjr input, PitCREWjr stops reading the input

FIFO for the balance of that transaction and issues an error

signal to the RACEway master on completion of the transac-

tion. The kill request is also sent in this case, so that the mas-

ter ends the transaction soon after the underflow. On comple-

tion of the RACEway data transfer, PitCREWjr deasserts the

“SLAVE” status output.

The intent of the “SLAVE” pin is to indicate a slave transaction

in progress. It can be used to tag incoming data, select a data

destination, or as a board logic control input.

Note that PitCREWjr will NOT cause route and address head-

er words received from the RACEway to be written to the out-

put FIFO. External logic would be required to place address

and/or route words in the output FIFO.

Master Function

The master function of PitCREWjr is accessed whenever the

“MGO” PitCREWjr input is asserted. The assertion of “MGO”

launches the PitCREWjr master state machine. This state

machine is clocked by the RACEway data clock “XCLKI”. Two

clocks after “MGO” is sampled asserted, PitCREWjr asserts

its “ROUTE” output. Local board hardware should use

“ROUTE” to enable a route word onto the FIFO data bus.

PitCREWjr asserts its “MASTER” output when it drives this

route word onto the RACEway and then drives the “shifted

route” prescribed by the RACEway protocol. “MGO” should

be deasserted once PitCREWjr’s “MASTER” output is true.

This is because “MGO” will cause a slave in progress to issue

a kill over the RACEway. When “change to address” reply is

received from the RACEway, “ROUTE” is deasserted, and

one clock later “ADDR” is asserted. Local board hardware

should use “ADDR” to enable an address word onto the FIFO

data bus. PitCREWjr relays the address word to the RACE-

way and waits for a “DSE

” reply from the RACEway. When the

reply is received, PitCREWjr deasserts the “ADDR” signal.

The RACEway protocol communicates data direction in bit 1

of the address word. PitCREWjr’s master state machine

branches on this bit value. If the direction of the data is from

the local FIFO to the RACEway (a master write, bit 1 of ad-

dress word is false), then data is read from the local input

FIFO, registered inside the PitCREWjr, and driven onto the

RACEway XBIO bus. The PitCREWjr FIFO data bus pins re-

main three-stated and PitCREWjr asserts the signals “IFRE

”

and “IFOE

” to enable the input FIFO data onto the FIFO data

bus. PitCREWjr asserts this signal pair each time a new word

is required from the FIFO. If the input FIFO becomes empty,

as signaled by the “IFAE

” PitCREWjr input, PitCREWjr stops

reading the input FIFO and ends the RACEway transaction.

If the direction of data is from the RACEway to the local FIFO

(a master read, bit 1 of address word is true), then as data

arrives from the RACEway, it is registered inside the Pit-

CREWjr and driven onto the FIFO data bus. The PitCREWjr

writes the data received from the RACEway to the output

FIFO by asserting “OFWEN” each time a valid word is ready

on the FIFO data bus. A PitCREWjr input called “OFAF

” is

used to indicate to PitCREWjr that the output FIFO is full.

Assertion of “OFAF

” causes PitCREWjr to suspend transfer

requests to the RACEway slave, effectively stalling the RACE-

way transaction until the signal is deasserted. “OFAF

” would

typically be connected to the output FIFO programmable al-

most full flag. On completion of the RACEway data transfer

Figure 3. PitCREWjr Signals

ADDR

ROUTE

MR_ERR

FIFO Data Bus

PitCREWjr

RACEway

SRE

FIFO Cntl

FIFOs

SLAVE

MGO

COUNT

MASTER

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