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Pentek Model 6526 Operating Manual Page 23
Rev. A
2.4 Model 6526 Front Panel
The front panel of Pentek’s Model 6526 is shown in Figure 2−6, at
the right. Available on the front panel are an 80−pin Digital Data
In connector, a Reset button, a 14−pin Sync bus connector, several
indicator LEDs, and a 20−pin Serial connector for access to the
TMS320C31’s Serial Port. Each of these is described in a subsec−
tion below.
2.4.1 Digital Data Input Connector
The input connector, labeled DIGITAL DATA IN, is an
80−pin flat ribbon cable header manufactured by 3M.
The part number for the header is 3M #81080−620203
(Pentek part # 354.08001).
The mating flat cable socket connector is 3M #82080−
6006, and the strain relief is 3M #3858−080. Pentek’s
part number for the connector, with the strain relief, is
353.08005. One of each of these items is supplied with
the Model 6526. The recommended 0.025" pitch flat rib−
bon cable is 3M #3756/80.
A 68−conductor cable of the same type may also be used
for applications requiring only 12 data bits. This cable is
type 3M #3756/68. The 68−conductor cable should be
crimped into the center of the 80−pin cable connector
such that pins 1 through 6 and pins 75 through 80 are
left unconnected.
The 80−pin connector is composed of two similar
40−pin groups, one for each input signal. The ribbon
cable can be split in half, forming two 40−pin cables.
The pin assignment for the connector is shown on the
next page, in Figure 2−7, for the two input signal
options.
• Model 6526 Option 002 accommodates two 16−bit
differential ECL−level input signals, available from
such devices as Pentek A/D Converter Models 6402
Option 002, 6410 Option 002, 6425 Option 001, 6441
Option 002, 6465, 6470, and 6472.
• Model 6526 Option 019 accepts single−ended TTL−
level signals, and is compatible with the standard
versions of Pentek A/D Converter Models 6402,
6410, 6420, 6425, and 6441.
Figure 2−6:
Model 6526
Front Panel
RESET
TCK1
S
Y
N
C
S
E
R
I
A
L
D
I
G
I
T
A
L
D
A
T
A
I
N
TCK0
XF1
XF0
FSX0
DX0
CKX0
FSR0
DR0
CKR0
A
B
A
B
MASTER
SYNC
TERM
DSP
FAIL
MASTER
RACEWAY
CLOCK
OVLD
+
- PENTEK MODEL 6526 1
- Copyrights 2
- Trademarks 2
- Manual Revision History 2
- Warranty 2
- Table of Contents 10
- Chapter 1: Overview 11
- 1.6 Channel Formatters 12
- 1.4 Time Stamp Counter 12
- 1.5 Command Controller / DSP 12
- 1.7 RACEway Interface 13
- 1.8 Digital Interfaces 13
- 1.9 VMEbus Interface 13
- 1.10 Model 6526 Block Diagram 14
- 1.11 Specifications 15
- 2.1 Inspection 17
- Pin 1 – Pin 2* Disabled* 22
- Pin 2 – Pin 3 Enabled 22
- * Factory Default Setting 22
- 2.4 Model 6526 Front Panel 23
- 2.4.2 Sync Bus 27
- 2.4.2.1 Sync Bus Connector 27
- 2.4.2 Sync Bus (continued) 28
- 2.4.3 TMS320C31 Serial Port 31
- 2.4.4 Reset Button 31
- CAUTION!! 33
- 3.1 Programming Overview 35
- 3.3 VMEbus Access 36
- 3.4 VMEbus A16 Slave Memory 37
- 3.4.1.2 DSP Reset − Bit D1 38
- 3.6.13.1 Lock Flag − Bit D0 86
- 3.6.13.2 Read Flag − Bit D1 86
- 3.7.1.1 Single Load − Bit D0 94
- 3.7.5 Command Set 98
- (continued) 100
- 3.8.1.1 BIST Fail − Bit D0 103
- 3.8.1.2 DSP LED − Bit D9 103
- Sync_Source bit SYNC 107
- B.1 Overview 133
- B.2 RACEway ILK1 133
- B.3 RACEway ILK 4 Example 133
- B.4 RACEway ILK 8 Example 134
- B.5 RACEway ILK12 Example 136
- B.6 RACEway ILK16 Example 137
- Appendix C: Graychip 4014 139
- Rev.: A 140
- GRAYCHIP 141
- “NARROW*1.97” 142
- “NARROW*0.97 + 1" 142
- GC4014 DATASHEET 146
- 3.0 FUNCTIONAL DESCRIPTION 147
- 3.1 CONTROL INTERFACE 147
- READ CYCLE- RD HELD LOW 148
- WRITE CYCLE- RD 148
- HELD LOW 148
- 3.3 THE DOWN CONVERTERS 149
- Figure 4. NCO Circuit 150
- Figure 5. Example NCO Spurs 150
- 3.3.2 Four Stage CIC Filter 151
- 3.3.3 Coarse Channel Gain 152
- (c) GSM Coefficients 153
- ∞ to +24 dB in 154
- 3.6 OUTPUT MODES 155
- 3.6.2 Serial Outputs 155
- Table 2: TDM Modes 155
- 3.6.3 Link Mode Output 156
- 3.7 CLOCKING 157
- 3.8 POWER DOWN MODES 157
- 3.9 SYNCHRONIZATION 157
- 3.10 DATA LATENCY 158
- 3.11 DIAGNOSTICS 158
- Table 3: Latency 158
- 4.0 PACKAGING 159
- GC4014-PQ 159
- QUAD RCVR 159
- MMMMMM LLL 159
- GRAYCHIP YYWW 159
- 5.0 CONTROL REGISTERS 161
- 5.1 SYNC MODE REGISTER 162
- Table 4: Sync Modes 162
- 5.2 DECIMATION MODE REGISTER 163
- 5.3 CIC DECIMATION REGISTERS 163
- 5.4 SCALE CONTROL REGISTER 164
- 5.5 CHANNEL GAIN REGISTER 164
- 5.6 OUTPUT FORMAT REGISTER 165
- 5.7 OUTPUT MODE REGISTER 165
- 5.8 BLANKING CONTROL REGISTER 165
- 5.10 COUNTER MODE REGISTERS 166
- 5.11 TEST MODE REGISTER 167
- 5.12 PAGE MAP REGISTER 167
- 5.13 STATUS CONTROL REGISTER 168
- 5.14 CHECKSUM REGISTER 168
- Table 5: Mask Revisions 169
- , suggested default = 0x80 170
- , suggested default = 0x5f 171
- 6.4 DC CHARACTERISTICS 174
- 6.5 AC CHARACTERISTICS 175
- GSM Blocker Requirements 177
- Table 11: GSM Configuration 178
- DAMPS Blocker Requirements 179
- PFIR_SUM 180
- 7.7 DIAGNOSTICS 181
- 7.8 OUTPUT TEST CONFIGURATION 183
- SCALE 6 BIG_SCALE× 56–+() 184
- Appendix D: PitCREWjr 185
- Master Writes and Slave Reads 187
- Master Reads and Slave 187
- Figure 2 189
- Master Function 189
- Figure 4 190
- Figure 5 190
- Figures 6 190
- Figure 5. Master Read 191
- Figure 6. Slave Write 191
- Figure 8 192
- Figure 9 192
- Figure 10 192
- Figure 9. SRE Function 194
- Figure 10. Master Read Error 195
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