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Pentek Model 6526 Operating Manual Page 7
Page
Table of Contents
Rev. A
Chapter 3: Memory Maps and Register Descriptions (continued)
3.6 VMEbus A24/A32 Channel Formatter Register Memory............................................................68
Table 3−28: VMEbus A24/A32 Channel Formatter Register Memory Map ...........................68
Table 3−29: ‘C31 Address Ranges for Channel Formatter Registers .......................................69
3.6.1 RACEway Data Packet Structure ...................................................................................69
Table 3−30: RACEway Data Packet Structure.............................................................69
3.6.2 Packet Start Code Register ................................................................................................... 71
Table 3−31: Packet Start Code Register ........................................................................71
3.6.3 Channel n ID Tag Registers ................................................................................................. 71
Table 3−32: Channel n ID Tag Registers......................................................................71
3.6.3.1 Destination Processor ID ..............................................................................72
3.6.3.2 Destination Board ID ....................................................................................72
3.6.3.3 Source DDR Channel ID ..............................................................................72
3.6.3.4 Source DDR Board ID ...................................................................................72
3.6.4 Channel n Block Counter Output Register ....................................................................... 73
Table 3−33: Channel n Block Counter Output Register............................................73
3.6.5 Time Stamp Counter Output Register ...........................................................................73
Table 3−34: Time Stamp Counter Output Register....................................................73
3.6.6 Channel n DDR Complex Output Data Register .........................................................74
Table 3−35: Channel n DDR Complex Data Output Register .................................74
3.6.6.1 DDR Output Data: In−Phase (Real) Component .....................................74
3.6.6.2 DDR Output Data: Quadrature (Imaginary) Component ......................74
3.6.7 Packet Stop Code Register................................................................................................75
Table 3−36: Packet Stop Code Register ........................................................................75
3.6.8 Channel n Formatter Status Register..............................................................................75
Table 3−37: Channel n Formatter Status Register ......................................................75
3.6.8.1 RACEway FIFO Full .....................................................................................76
3.6.8.2 Packet Send Request .....................................................................................76
3.6.8.3 Sync Word Substitution Armed...................................................................76
3.6.8.4 Block Counter Synchronous Reset Armed ................................................76
3.6.9 Channel n Formatter Control Register ..........................................................................77
Table 3−38: Channel n Formatter Control Register ...................................................77
3.6.9.1 Sync Word Substitution Enable ..................................................................77
3.6.9.2 Block Counter Synchronous Reset Enable ................................................78
3.6.9.3 Packet Output Enable ...................................................................................78
3.6.9.4 Channel Formatter Enable ...........................................................................79
3.6.9.5 Mode Selection ..............................................................................................79
3.6.9.6 Packet Start Delay .........................................................................................80
3.6.9.7 Number of Packets per Trigger ...................................................................80
3.6.10 Channel n RACEway Packet Size Register .......................................................................81
Table 3−39: Channel n RACEway Packet Size Register............................................81
Table 3−40: Channel n RACEway Packet Size Register − Packet Size Settings ..81
3.6.11 Channel n Sync Code Word Register .............................................................................82
Table 3−41: Channel n Sync Code Word Register .....................................................82
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