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GRAYCHIP, INC. - 33 - APRIL 27, 1999
GC4014 QUAD RECEIVER CHIP DATA SHEET REV 0.5
This document contains information which may be changed at any time without notice
The suggested GSM control register settings for the chip with an input sample rate of 54.166 MHz (N=25)
is shown in Table 12 (other input rates can be used up to 62.5 MHz, 54.166 is used as an example):
The variables SCALE, BIG_SCALE (address 4) and G (address 16
HEX
of pages 4,5,6,and 7) are set as
follows. The values of SCALE and BIG_SCALE must be set to satisfy: . N is
25, so (4log
2
N) is 37.14. This means , which is satisfied by setting SCALE=1 and
BIG_SCALE=6. SCALE, however, needs to be decreased to 0 to prevent overflow in the CFIR, which has a gain of
1.97. The overall gain is set using “G” according to:
Where COARSE is 0 and PFIR_SUM is 125151. The optimal setting of GAIN is 2.0 in order to compensate for the
loss in the tuning process (See Section 7.9). A value of G=46 (2E
HEX
) will give a gain of 2.015.
The output serial format is set in address 6 to have a bit rate of one half the chip’s clock rate and to be used
in the packed mode. The user will need to configure the output format as is necessary for the application.
Table 11: GSM Configuration
Control Registers Channel pages 4,5,6,7 Coefficient Pages
Address Data Address Data Page 8 Page 9 Page 10 Page 11
00 (HEX) 65 (HEX)
1
10 (HEX) FREQ[0:7] EF F1 74 66
01 80->82
2
11 FREQ[8:15] 03 FD 08 F5
02 19 12 FREQ[16:23] C3 CD D5 86
03 00 13 FREQ[24:31] F8 FA 07 00
04 60 14 00 (HEX) 4F 52 CB A3
05 00 15 00 00 FA 05 0F
06 11 16 2E 0F C1 3D A9
07 00 17 00 07 FB 00 20
08 50 18 5F 61 2F 24 86
09 55 19 06 FD F9 32
0A FF 1A A7 6B C2 71
0B FF 1B 01 FF F3 42
0C 08 1C 09 F0 8F 6D
0D 1P
3
1D 01 03 F0 4C
0E 00 1E AF C1 50 81
0F read only 1F 00 07 F0 4F
1. Initialize to 65 while configuring the chip(s), then set to E5, then back to 65 to fire off the one-shot sync.This
assumes that SO
is tied to SI
2. Initialize to 80, then set to 82 after external coefficients are loaded.
3. “P” is the page number. The upper nibble should stay at “1¨.
SCALE 6 BIG_SCALE×+()56 4log
2
N–()≤
SCALE 6 BIG_SCALE×+()37≤
GAIN 25
4
2
36 56–()
{} 2
COARSE
[]1.97{}
PFIR_SUM
65536
-------------------
{}
G
32
------
0.0438G==
- PENTEK MODEL 6526 1
- Copyrights 2
- Trademarks 2
- Manual Revision History 2
- Warranty 2
- Table of Contents 10
- Chapter 1: Overview 11
- 1.6 Channel Formatters 12
- 1.4 Time Stamp Counter 12
- 1.5 Command Controller / DSP 12
- 1.7 RACEway Interface 13
- 1.8 Digital Interfaces 13
- 1.9 VMEbus Interface 13
- 1.10 Model 6526 Block Diagram 14
- 1.11 Specifications 15
- 2.1 Inspection 17
- Pin 1 – Pin 2* Disabled* 22
- Pin 2 – Pin 3 Enabled 22
- * Factory Default Setting 22
- 2.4 Model 6526 Front Panel 23
- 2.4.2 Sync Bus 27
- 2.4.2.1 Sync Bus Connector 27
- 2.4.2 Sync Bus (continued) 28
- 2.4.3 TMS320C31 Serial Port 31
- 2.4.4 Reset Button 31
- CAUTION!! 33
- 3.1 Programming Overview 35
- 3.3 VMEbus Access 36
- 3.4 VMEbus A16 Slave Memory 37
- 3.4.1.2 DSP Reset − Bit D1 38
- 3.6.13.1 Lock Flag − Bit D0 86
- 3.6.13.2 Read Flag − Bit D1 86
- 3.7.1.1 Single Load − Bit D0 94
- 3.7.5 Command Set 98
- (continued) 100
- 3.8.1.1 BIST Fail − Bit D0 103
- 3.8.1.2 DSP LED − Bit D9 103
- Sync_Source bit SYNC 107
- B.1 Overview 133
- B.2 RACEway ILK1 133
- B.3 RACEway ILK 4 Example 133
- B.4 RACEway ILK 8 Example 134
- B.5 RACEway ILK12 Example 136
- B.6 RACEway ILK16 Example 137
- Appendix C: Graychip 4014 139
- Rev.: A 140
- GRAYCHIP 141
- “NARROW*1.97” 142
- “NARROW*0.97 + 1" 142
- GC4014 DATASHEET 146
- 3.0 FUNCTIONAL DESCRIPTION 147
- 3.1 CONTROL INTERFACE 147
- READ CYCLE- RD HELD LOW 148
- WRITE CYCLE- RD 148
- HELD LOW 148
- 3.3 THE DOWN CONVERTERS 149
- Figure 4. NCO Circuit 150
- Figure 5. Example NCO Spurs 150
- 3.3.2 Four Stage CIC Filter 151
- 3.3.3 Coarse Channel Gain 152
- (c) GSM Coefficients 153
- ∞ to +24 dB in 154
- 3.6 OUTPUT MODES 155
- 3.6.2 Serial Outputs 155
- Table 2: TDM Modes 155
- 3.6.3 Link Mode Output 156
- 3.7 CLOCKING 157
- 3.8 POWER DOWN MODES 157
- 3.9 SYNCHRONIZATION 157
- 3.10 DATA LATENCY 158
- 3.11 DIAGNOSTICS 158
- Table 3: Latency 158
- 4.0 PACKAGING 159
- GC4014-PQ 159
- QUAD RCVR 159
- MMMMMM LLL 159
- GRAYCHIP YYWW 159
- 5.0 CONTROL REGISTERS 161
- 5.1 SYNC MODE REGISTER 162
- Table 4: Sync Modes 162
- 5.2 DECIMATION MODE REGISTER 163
- 5.3 CIC DECIMATION REGISTERS 163
- 5.4 SCALE CONTROL REGISTER 164
- 5.5 CHANNEL GAIN REGISTER 164
- 5.6 OUTPUT FORMAT REGISTER 165
- 5.7 OUTPUT MODE REGISTER 165
- 5.8 BLANKING CONTROL REGISTER 165
- 5.10 COUNTER MODE REGISTERS 166
- 5.11 TEST MODE REGISTER 167
- 5.12 PAGE MAP REGISTER 167
- 5.13 STATUS CONTROL REGISTER 168
- 5.14 CHECKSUM REGISTER 168
- Table 5: Mask Revisions 169
- , suggested default = 0x80 170
- , suggested default = 0x5f 171
- 6.4 DC CHARACTERISTICS 174
- 6.5 AC CHARACTERISTICS 175
- GSM Blocker Requirements 177
- Table 11: GSM Configuration 178
- DAMPS Blocker Requirements 179
- PFIR_SUM 180
- 7.7 DIAGNOSTICS 181
- 7.8 OUTPUT TEST CONFIGURATION 183
- SCALE 6 BIG_SCALE× 56–+() 184
- Appendix D: PitCREWjr 185
- Master Writes and Slave Reads 187
- Master Reads and Slave 187
- Figure 2 189
- Master Function 189
- Figure 4 190
- Figure 5 190
- Figures 6 190
- Figure 5. Master Read 191
- Figure 6. Slave Write 191
- Figure 8 192
- Figure 9 192
- Figure 10 192
- Figure 9. SRE Function 194
- Figure 10. Master Read Error 195
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