VXI?Corporation F80 Especificaciones descargar pdf (Pagina 54)

Page 54 Pentek Model 6526 Operating Manual

Rev. A

3.5 VMEbus A24/A32 Global Slave Register Memory (continued)

3.5.6 RACEway Status Register (continued)

3.5.6.7 Master Error − Bit D9

The PitCREW RACEway controller will set this bit to the logic '1'

state when it has encountered an error during a master read trans−

action. This bit will read back in its default logic '0' state under all

other circumstances.

3.5.6.8 Diagnostics − Bits D15 to D11

These five bits are included for factory diagnostic purposes. The

Request Flag Found bit (D11) is set to the logic '1' state whenever a

receiver channel sets its request flag bit in this register (see Section

3.5.6.9, below). Under all other conditions, this bit will read back

in its default logic '0' state.

The other four diagnostic bits (D15 to D12) comprise a field that

indicates the state of the Model 6526’s state machine. These four

bits may be masked or simply ignored when reading this register.

3.5.6.9 Channel Request − Bits D31 to D16

This field contains one bit associated with each digital receiver

channel on the Model 6526. The RQn bit is set to the logic '1' state

when receiver channel n has data ready to be transmitted over the

RACEway interface, where 'n' is the channel number from 0 to 15

(e. g., receiver channel 9 will set the RQ9 bit). Note that any or all

of these bits may be set simultaneously. When one of these bits is

in its default logic '0' state, the associated receiver channel does not

have data ready for RACEway transmission.

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VXI?Corporation F80 Especificaciones Pagina 54