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Pentek Model 6526 Operating Manual Page 41

Rev. A

3.4 VMEbus A16 Slave Memory (continued)

3.4.2 Sync Bus Control Register − R/W @ A16_base+0x04

Only two bits of this register are active. One bit is used to enable the Model

6526 as a sync bus master, and the other is used to enable the 6526 as a sync

bus terminator. Table 3−4, below, shows the placement of these bits. The

subsections following the table describe these bits.

3.4.2.1 Sync Bus Master − Bit D0

When this bit is set to the logic '1' state, the Low Voltage TTL bus

drivers for the front panel Sync bus connector are activated. This

function should be enabled only for one Model 6526 in a group of

6526s sharing a common Sync bus, and the enabled board should

be located at one end of the front panel ribbon cable. All other

devices connected to that Sync bus should be slaves, which means

that this bit should be cleared to the logic '0' state (its default con−

dition) in those devices.

3.4.2.2 Sync Bus Termination − Bit D1

When this bit is set to the logic '1' state, the active termination cir−

cuitry for the front panel Sync bus is activated. This function

should be enabled only for one Model 6526 in a group of 6526s

sharing a common Sync bus, and the enabled board should be at

the opposite end of the front panel ribbon cable from the Sync bus

master (see Section 3.4.2.1, above). All other devices connected to

that Sync bus should have the termination disabled, which means

that this bit should be cleared to the logic '0' state (its default con−

dition) in those devices.

Table 3−4: Sync Bus Control Register

R/W @ A16_base+0x04

Bit # D15 − D2 D1 D0

Bit Name R e s e r v e d − N o t U s e d

Sync

_Term

Sync_

Master

Function

W r i t e w i t h z e r o s ,

M a s k w h e n r e a d i n g

1 = Enable

0 = Disable

1 = Master

0 = Slave

All bits default to the logic '0' state at power up

1 2 ... 36 37 38 39 40 41 42 43 44 45 46 ... 195 196

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VXI?Corporation F80 Especificaciones Pagina 41