VXI?Corporation F80 Especificaciones Pagina 62

  • Descarga
  • Añadir a mis manuales
  • Imprimir
  • Pagina
    / 196
  • Tabla de contenidos
  • MARCADORES
  • Valorado. / 5. Basado en revisión del cliente
Vista de pagina 61
Page 62 Pentek Model 6526 Operating Manual
Rev. A
3.5 VMEbus A24/A32 Global Slave Register Memory (continued)
3.5.13 Input FIFO A Control Register (continued)
3.5.13.2 Write Mode − Bits D3 to D2
These two bits determine when and how data can be written to
Input FIFO A. When both of these bits are cleared to the logic '0'
state, Input FIFO A is ready to accept data (or is accepting data),
and will remain writeenabled until the state of bit D3 changes.
When D3 is set to the logic '1' state (regardless of the state of D2),
the FIFO write is disabledall data in FIFO A at the time of this
transition is retained, but no further data is accepted. When bit D2 is
set to the logic '1' state and D3 is a logic '0', Input FIFO A is write−
enabled when SYNC0 goes to a logic '1'.
3.5.13.3 Read Mode − Bits D5 to D4
These two bits determine when and how data can be read from
Input FIFO A. When both of these bits are cleared to the logic '0'
state, Input FIFO A is ready to output data (or is outputting data).
When both bits are set to the logic '1' state, the FIFO read is dis−
abled all data in FIFO A is retained and data is accepted until the
FIFO is filled, but no data may be read from the FIFO.
When bit D4 is set to logic '1' and D5 is a logic '0', Input FIFO A is
readenabled after the delay set in the Input FIFO A Delay Control
Register has elapsed following the assertion of the SYNC0 signal
(see Section 3.5.11). When bit D5 is set to logic '1' and D4 is a logic
'0', Input FIFO A is read−enabled after the delay set in the Input
FIFO B Delay Control Register has elapsed following the assertion
of the SYNC1 signal (see Section 3.5.12).
Table 3−22: Input FIFO A Write Mode
D3 D2 Write Mode
0 0 Write Enabled (default after reset)
0 1 Write Enabled on Sync0
1 Don’t Care Write Disabled
Table 3−23: Input FIFO A Read Mode
D5 D4 Read Mode
0 0 Read Enabled (default after reset)
0 1 Read Enabled on FIFO A Delay after Sync0
1 0 Read Enabled on FIFO B Delay after Sync1
1 1 Read Disabled
Vista de pagina 61
1 2 ... 57 58 59 60 61 62 63 64 65 66 67 ... 195 196

Comentarios a estos manuales

Sin comentarios